{"product_id":"mf172600-semi-mf1726-practice-for-analysis-of-crystallographic-perfection-of-silicon-wafers","title":"MF172600 - SEMI MF1726 - Practice for Analysis of Crystallographic Perfection of Silicon Wafers","description":"\u003cp dir=\"ltr\" align=\"justify\"\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp dir=\"ltr\" align=\"justify\"\u003e\u003c\/p\u003e\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eEpitaxial growth processes are used extensively in the\nmanufacture of silicon electronic devices. Stacking faults introduced during\nepitaxial growth can cause ‘soft’ electrical characteristics and preferential\nmicro plasma breakdowns in diodes.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eEpitaxial defects are more clearly delineated with the use\nof this destructive etching procedure. Epitaxial wafers may however be\nclassified nondestructively by this method without the destructive preferential\netching and inspection steps.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Practice provides guidance regarding procedures for\nanalysis of crystal defects of silicon ingots from which silicon wafers are\ncut.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Practice, together with the referenced standards, may\nbe used for process control, research and development, and material acceptance\npurposes.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cbr\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Practice covers the determination of the density of\ncrystallographic defects in unpatterned polished and epitaxial silicon wafers.\nEpitaxial silicon wafers may exhibit dislocations, hillocks, shallow pits or\nepitaxial stacking faults, while polished wafers may exhibit several forms of\ncrystallographic defects or surface damage. Use of this Practice is based upon\nthe application of several referenced standards in a prescribed sequence to\nreveal and count microscopic defects or structures.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Practice is suitable for use with epitaxial or\npolished wafers grown in either [111] or [100] direction and doped either p- or\nn-type with resistivity greater than 0.005 Ω·cm.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Practice is suitable for use with epitaxial wafers\nwith layer thickness greater than 0.5 µm.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eAdditional requirements on the material to be tested are\nlisted in SEMI MF1810.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e (purchase separately)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M59 — Terminology for Silicon Technology\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF95 — Test Method for Thickness of Lightly Doped\nSilicon Epitaxial Layers on Heavily Doped Silicon Substrates Using an Infrared\nDispersive Spectrophotometer\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF523 — Practice for Unaided Visual Inspection of\nPolished Silicon Wafers Surfaces\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1809 — Guide for Selection and Use of Etching\nSolutions to Delineate Structural Defects in Silicon\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1810 — Test Method for Counting Preferentially\nEtched or Decorated Surface Defects in Silicon Wafers\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eRevision History\u003c\/b\u003e\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1726-1110 (Reapproved 0322)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1726-1110 (Reapproved 1115)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1726-1110 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1726-1103 (first SEMI publication)\u003c\/span\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI MF1726-1110 (Reapproved 0322) - Current","offer_id":40234293755971,"sku":"14933","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI MF1726-1110 (Reapproved 1115) - Superseded","offer_id":40234293788739,"sku":"4942","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI MF1726-1110 - Superseded","offer_id":40234293821507,"sku":"9893","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI MF1726-1103 - Superseded","offer_id":40234293854275,"sku":"9892","price":31900.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/MFVolume_76baf0ab-55c1-488f-8e3f-1de379aa55c8.png?v=1776702534","url":"https:\/\/store-dev2.semi.org\/en-jp\/products\/mf172600-semi-mf1726-practice-for-analysis-of-crystallographic-perfection-of-silicon-wafers","provider":"SEMI Dev 2","version":"1.0","type":"link"}