{"product_id":"mf115200-semi-mf1152-test-method-for-dimensions-of-notches-on-silicon-wafers","title":"MF115200 - SEMI MF1152 - Test Method for Dimensions of Notches on Silicon Wafers","description":"\u003cp dir=\"ltr\" align=\"justify\"\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp dir=\"ltr\" align=\"justify\"\u003e\u003c\/p\u003e\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eWafers must be accurately aligned in various processing\nequipment during integrated circuit manufacture.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eA notch ground into the edge of the wafer at a specified\norientation provides a positive method for such alignment. The accuracy of the\ncritical dimensions of the notch controls the possible accuracy of the\nalignment.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Test Method may be used for process control, quality\ncontrol, and incoming or outgoing inspection.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eUntil an index of precision is determined based on an interlaboratory\nevaluation, this Test Method is not recommended for use in decisions between\npurchasers and suppliers.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cbr\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Test Method covers a nondestructive procedure to\ndetermine whether or not the dimensions, except for the blend radius, of fiducial\nnotches on silicon wafers fall within specified limits.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Test Method is specifically directed to the notch\ndimensions specified in SEMI M1, but with suitable modifications, the\nprinciples of this test method may be applied to any desired notch dimensions.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eNo test is provided for the blend radius at the apex of the\nnotch.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThe values stated in SI units are to be regarded as the\nstandard. The values given in parentheses are for information only.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e (purchase separately)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M1 — Specification for Polished Single Crystal Silicon\nWafers\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eRevision History\u003c\/b\u003e\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1152-0316 (Reapproved 0222)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1152-0316 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1152-0305 (Reapproved 0211)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1152-0305 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1152-02 (first SEMI publication)\u003c\/span\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI MF1152-0316 (Reapproved 0222) - Current","offer_id":40234289496131,"sku":"14895","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI MF1152-0316 - Superseded","offer_id":40234289594435,"sku":"4919","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI MF1152-0305 (Reapproved 0211) - Superseded","offer_id":40234289659971,"sku":"9802","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI MF1152-0305 - Superseded","offer_id":40234289758275,"sku":"9801","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI MF1152-02 - Superseded","offer_id":40234289922115,"sku":"9800","price":31900.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/MFVolume_3040f924-95fe-4c20-a960-7306a360f5bf.png?v=1776702567","url":"https:\/\/store-dev2.semi.org\/en-jp\/products\/mf115200-semi-mf1152-test-method-for-dimensions-of-notches-on-silicon-wafers","provider":"SEMI Dev 2","version":"1.0","type":"link"}