{"product_id":"m05700-semi-m57-specification-for-silicon-annealed-wafers","title":"M05700 - SEMI M57 - Specification for Silicon Annealed Wafers","description":"\u003cp dir=\"ltr\" align=\"justify\"\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp dir=\"ltr\" align=\"justify\"\u003e\u003c\/p\u003e\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eA number of device manufacturers utilize silicon annealed\nwafers to gain improved device characteristics. This Specification provides\ninformation for developing specifications for silicon annealed wafers used to\nfabricate semiconductor devices and integrated circuits.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cbr\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Specification covers dimensional, electrical,\nchemical, and structural properties of silicon annealed wafers for 180 nm,\n130 nm, 90 nm, (Table R1-1), 65 nm, 45 nm, 32 nm, (Table R1-2), and 22 nm\n(Table R1-3) device technology generations.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eBased on the guidance herein, the user of this Document can\ngenerate specifications for silicon annealed wafers.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eOne of the reasons for using annealed wafers is to allow a\nreduction in the crystal originated pits (COP), also sometimes known as crystal\noriginated particles, near the top surface region of the wafer. The width of\nthe denuded zone (DZ) free of bulk micro defects (BMD) is also an important\nparameter.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e (purchase separately)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M1 — Specification for Polished Single Crystal Silicon\nWafers\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M35 — Guide for Developing Specifications for Silicon\nWafer Surface Features Detected by Automated Inspection\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M45 — Specification for 300 mm Wafer Shipping System\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M53 — Practice for Calibrating Scanning Surface\nInspection Systems Using Certified Depositions of Monodisperse Reference Spheres\non Unpatterned Semiconductor Wafer Surfaces\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M58 — Test Method for Evaluating DMA Based Particle\nDeposition Systems and Processes\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M59 — Terminology for Silicon Technology\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF81 — Test Method for Measuring Radial Resistivity\nVariation on Silicon Wafers\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF391 — Test Methods for Minority Carrier Diffusion\nLength in Extrinsic Semiconductors by Measurement of Steady-State Surface\nPhotovoltage\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF523 — Practice for Unaided Visual Inspection of\nPolished Silicon Wafer Surfaces\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF951 — Test Method for Determination of Radial\nInterstitial Oxygen Variation in Silicon Wafers\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1239 — Test Method for Oxygen Precipitation\nCharacteristics of Silicon Wafers by Measurement of Interstitial Oxygen\nReduction\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1530 — Test Method for Measuring Flatness,\nThickness, and Total Thickness Variation on Silicon Wafers by Automated\nNoncontact Scanning\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1535 — Test Method for Carrier Recombination\nLifetime in Electronic-Grade Silicon Wafers by Noncontact Measurement of\nPhotoconductivity Decay by Microwave Reflectance\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1617 — Test Method for Measuring Surface Sodium,\nAluminum, Potassium, and Iron on Silicon and EPI Substrates by Secondary Ion\nMass Spectroscopy\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1726 — Practice for Analysis of Crystallographic\nPerfection of Silicon Wafers\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1727 — Practice for Detection of Oxidation Induced\nDefects in Polished Silicon Wafers\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MF1809 — Guide for Selection and Use for Etching\nSolutions to Delineate Structural Defects in Silicon\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI T3 — Specification for Wafer Box Labels\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI T7 — Specification for Back Surface Marking of\nDouble-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eRevision History\u003c\/b\u003e\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-0316 (Reapproved 1021)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-0316 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-0414 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-0413 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-1011 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-0706 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-0705 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-0305 (complete rewrite)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M57-0704 (first published)\u003c\/span\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI M57-0316 (Reapproved 1021) - Current","offer_id":40234292576323,"sku":"14741","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI M57-0316 - Superseded","offer_id":40234292641859,"sku":"4871","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI M57-0414 - Superseded","offer_id":40234292674627,"sku":"9667","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI M57-0413 - Superseded","offer_id":40234292707395,"sku":"9665","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI M57-1011 - Superseded","offer_id":40234292740163,"sku":"9672","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI M57-0706 - Superseded","offer_id":40234292772931,"sku":"9670","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI M57-0705 - Superseded","offer_id":40234292805699,"sku":"9669","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI M57-0305 - Superseded","offer_id":40234292838467,"sku":"9664","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI M57-0704 - Superseded","offer_id":40234292871235,"sku":"9668","price":31900.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/MVolume_cf91d0b0-3888-447e-aa76-ee6b536e5b75.png?v=1776702604","url":"https:\/\/store-dev2.semi.org\/en-jp\/products\/m05700-semi-m57-specification-for-silicon-annealed-wafers","provider":"SEMI Dev 2","version":"1.0","type":"link"}