{"product_id":"3d01800-semi-3d18-guide-for-wafer-edge-trimming-for-3ds-ic-process","title":"3D01800 - SEMI 3D18 - Guide for Wafer Edge Trimming for 3DS-IC Process","description":"\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e3DS-IC wafer edge trimming process is a key step for successful wafer thinning after the wafer bonded in the 3DS-IC process.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e\u003cbr\u003e\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e \u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Guide provides a feasible approach to perform the wafer edge trimming.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e\u003cbr\u003e\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e \u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Document provides guidance for specifying edge trimming and resultant particle count to ensure the successful wafer thinning process after the wafer edge trimming.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e\u003cbr\u003e\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e \u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Document covers guidance for specifying wafer edge trimming and resultant particle count to provide a feasible approach in edge trimming process.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e\u003cbr\u003e\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e \u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThe trimming width, depth, and resultant particle size and count are addressed in this Guide. The outcome of this applicable wafer edge trimming approach will be helpful to the subsequent wafer thinning process in the 3DS-IC process.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e\u003cbr\u003e\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003c\/p\u003e\u003cp dir=\"ltr\" align=\"justify\"\u003e \u003c\/p\u003e\u003cfont face=\"arial\" size=\"2\"\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e\u003cbr\u003e\u003c\/font\u003e\u003cp\u003e\u003cfont face=\"arial\" size=\"2\"\u003eSEMI 3D6 — Guide for CMP and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration\u003c\/font\u003e\u003cbr\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI 3D18-1018 - Current","offer_id":40234233364547,"sku":"999","price":31900.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/3DVolume_d2e0bc91-b679-40de-bd25-abf091e9e90f.png?v=1776703135","url":"https:\/\/store-dev2.semi.org\/en-jp\/products\/3d01800-semi-3d18-guide-for-wafer-edge-trimming-for-3ds-ic-process","provider":"SEMI Dev 2","version":"1.0","type":"link"}