{"product_id":"3d00700-semi-3d7-guide-for-alignment-mark-for-3ds-ic-process","title":"3D00700 - SEMI 3D7 - Guide for Alignment Mark for 3DS-IC Process","description":"\u003cp align=\"justify\"\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003c\/p\u003e\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003ePhoto alignment mark configuration is the key to ensure\nconsistent and precise alignment of layers, chips, and wafers. Therefore, this\nGuide provides the alignment mark strategy for chip to chip, chip to wafer, and\nwafer to wafer stacking. This Guide also addresses the universal alignment mark\nwhere the outcome will be a feasible photo alignment standard.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cbr\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eDefine and develop lithography alignment strategy for C2C, C2W\nand W2W stacking. The alignment mark is preferable to be implemented at frontside\nfinal metal and\/or backside metal layer masking. This Guide addresses universal\nalignment mark, including shape, dimension, and location. The outcome of a\nfeasible photo alignment standard will be critical to the C2C, C2W and W2W\nstacking.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e (purchase separately)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M20 — Practice for Establishing a Wafer Coordinate\nSystem \u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MS1 — Guide to Specifying Wafer-Wafer Bonding\nAlignment Targets\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eRevision History\u003c\/b\u003e\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI 3D7-0913 (Reapproved 0219)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI 3D7-0913 (first published)\u003c\/span\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI 3D7-0913 (Reapproved 0219) - Current","offer_id":40234242342979,"sku":"6170","price":31900.0,"currency_code":"JPY","in_stock":true},{"title":"SEMI 3D7-0913 - Superseded","offer_id":40234242375747,"sku":"1005","price":31900.0,"currency_code":"JPY","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/3DVolume_524bca2b-8387-426e-a436-5c5779e556ce.png?v=1776703143","url":"https:\/\/store-dev2.semi.org\/en-jp\/products\/3d00700-semi-3d7-guide-for-alignment-mark-for-3ds-ic-process","provider":"SEMI Dev 2","version":"1.0","type":"link"}