{"title":"Individual SEMI Standards","description":"","products":[{"product_id":"3d00800-semi-3d8-guide-for-describing-silicon-wafers-for-use-as-300-mm-carrier-wafers-in-a-3ds-ic-temporary-bond-debond-tbdb-process","title":"3D00800 - SEMI 3D8 - Guide for Describing Silicon Wafers for Use as 300 mm Carrier Wafers in a 3DS-IC Temporary Bond-Debond (TBDB) Process","description":"\u003cp align=\"justify\"\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003c\/p\u003e\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Guide is intended to address the needs of the 3D\nStacked IC (3DS-IC) industry by defining the items\/parameters needed to procure\nvirgin silicon carrier wafers to be used in a 3DS-IC process.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cbr\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Guide defines the items\/parameters to acquire silicon wafers\nto be used as carrier wafers in a temporary bond\/debond (TBDB) application.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eThis Guide describes silicon wafers with nominal diameter\nof 300 mm although, for 3DS-IC applications, the actual wafer diameter may differ\nslightly due to process requirements\u003ca name=\"_Toc215911941\"\u003e\u003c\/a\u003e\u003ca name=\"_Toc239666318\"\u003e\u003cspan style=\"mso-bookmark:_Toc215911941\"\u003e.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/a\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cspan style=\"mso-bookmark:_Toc215911941\"\u003e\u003c\/span\u003e\u003cspan style=\"mso-bookmark:_Toc239666318\"\u003e\u003c\/span\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e (purchase separately)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI 3D9 — Guide for Describing Materials Properties for a\n300 mm 3DS-IC Wafer Stack\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI 3D10 — Guide to Describing Materials Properties for\nIntermediate Wafers for Use in a 300 mm 3DS-IC Wafer Stack\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003c!--[if gte vml 1]\u003e\u003cv:line id=\"Straight_x0020_Connector_x0020_8\" style=\"position:absolute;z-index:251659264;visibility:visible;\n mso-wrap-style:square;mso-height-percent:0;mso-wrap-distance-left:9pt;\n mso-wrap-distance-top:0;mso-wrap-distance-right:9pt;\n mso-wrap-distance-bottom:0;mso-position-horizontal:absolute;\n mso-position-horizontal-relative:text;mso-position-vertical:absolute;\n mso-position-vertical-relative:page;mso-height-percent:0;\n mso-height-relative:margin\" from=\"-14.4pt,613.7pt\" to=\"-14.4pt,624.5pt\" strokecolor=\"black [3213]\" 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\u003cv:stroke joinstyle=\"miter\"\u003e\u003c\/v:stroke\u003e\n \u003cw:wrap anchory=\"page\"\u003e\u003c\/w:wrap\u003e\n\u003c\/v:line\u003e\u003c![endif]--\u003e\u003c!--[if !vml]--\u003e\u003cspan style=\"mso-ignore:vglayout;position:\nabsolute;z-index:251659264;margin-left:-21px;margin-top:816px;width:4px;\nheight:18px\"\u003e\u003cimg width=\"4\" height=\"18\" src=\"file:\/\/\/C:\/Users\/saustin\/AppData\/Local\/Temp\/msohtmlclip1\/01\/clip_image001.png\" v:shapes=\"Straight_x0020_Connector_x0020_8\"\u003e\u003c\/span\u003e\u003c!--[endif]--\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\"Arial\",sans-serif'\u003eSEMI\nM1 — Specification for Polished Single Crystal Silicon Wafers\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M45 — Specification for 300 mm Wafer Shipping System\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M59 — Terminology for Silicon Technology\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eRevision History\u003c\/b\u003e\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI 3D8-1121 (technical revision)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI 3D8-0514 (first published)\u003c\/span\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI 3D8-1121 - Current","offer_id":40234228252739,"sku":"14771","price":193.0,"currency_code":"USD","in_stock":true},{"title":"SEMI 3D8-0514 - Superseded","offer_id":40234228318275,"sku":"1006","price":193.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/3DVolume_d4ee1d3c-c083-47c2-b41a-5070fa449fd2.png?v=1776703143"},{"product_id":"3d00900-semi-3d9-guide-for-describing-materials-properties-for-a-300-mm-3ds-ic-wafer-stack","title":"3D00900 - SEMI 3D9 - Guide for Describing Materials Properties for a 300 mm 3DS-IC Wafer Stack","description":"\u003cp class=\"StdsText0\"\u003e \u003c\/p\u003e\u003cp\u003e1  Purpose\u003cbr\u003e1.1  This Guide is intended to address the needs of the 3D Stacked IC (3DS-IC) industry by providing the tools needed to procure wafer stacks to be used in a 3DS-IC process.\u003cbr\u003e2  Scope\u003cbr\u003e2.1  This Guide provides the tools to describe wafer stacks in a 3DS-IC process. A wafer stacking process takes two or more intermediate wafers and forms a stack, which can then be further processed as if it were a single wafer. After bonding the dimensions of the stack will no longer conform to standard thickness and\/or diameter.\u003cbr\u003e2.2  This Guide describes wafer stacks with nominal diameter of 300 mm, although the actual stack diameter may differ due to process and functional variation.\u003cbr\u003e2.2.1  The diameters of the different wafers that comprise the stack may differ from each other.\u003cbr\u003e\u003cstrong\u003eNOTICE:\u003c\/strong\u003e SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their use. It is the responsibility of the users of the Documents to establish appropriate safety and health practices, and determine the applicability of regulatory or other limitations prior to use.\u003c\/p\u003e\u003cp\u003e \u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eReferenced SEMI Standards\u003c\/strong\u003e (purchase separately)\u003cbr\u003eSEMI 3D4 — Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp\/Sori, and Flatness of Bonded Wafer Stacks\u003cbr\u003eSEMI M1 — Specification for Polished Single Crystal Silicon Wafers\u003cbr\u003eSEMI M45 — Specification for 300 mm Wafer Shipping System\u003cbr\u003eSEMI M59 — Terminology for Silicon Technology\u003cbr\u003eSEMI MF534 — Test Method for Bow of Silicon Wafers\u003cbr\u003eSEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning\u003cbr\u003eSEMI MF1390 — Test Method for Measuring Bow and Warp on Silicon Wafers by Automated Noncontact Scanning\u003cbr\u003eSEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning\u003cbr\u003eSEMI T7 — Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol\u003c\/p\u003e\u003cp\u003e \u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eRevision History\u003c\/strong\u003e\u003cbr\u003eSEMI 3D9-0914 (Reapproved 1025)\u003cbr\u003eSEMI 3D9-0914 (Reapproved 0420)\u003cbr\u003eSEMI 3D9-0914 (first published)\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI 3D9-0914 (Reapproved 1025) - Current","offer_id":43106911682627,"sku":"18794","price":193.0,"currency_code":"USD","in_stock":true},{"title":"SEMI 3D9-0914 (Reapproved 0420) - Superseded","offer_id":43106911715395,"sku":"13814","price":193.0,"currency_code":"USD","in_stock":true},{"title":"SEMI 3D9-0914 - Superseded","offer_id":40234230349891,"sku":"1007","price":193.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/3DVolume_b04b04f5-1d09-4f74-8b82-c16d0ca1bb1e.png?v=1776703142"},{"product_id":"3d01600-semi-3d16-specification-for-glass-base-material-for-semiconductor-packaging","title":"3D01600 - SEMI 3D16 - Specification for Glass Base Material for Semiconductor Packaging","description":"\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Specification is intended to address the needs of the 3D Stacked IC (3DS-IC) industry by providing the tools needed to procure glass as base material to be used in a 3DS-IC process or in similar applications. Such glass may be specified with or without openings for through glass vias (TGV) or blind vias (BV).\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e \u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Specification describes dimensional and thermal characteristics of glass base material for interposers, RF devices, and other similar packaging substrates.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e \u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Specification also applies to openings in glass.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e \u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThe glass substrate is in shape of a wafer (round) or a panel (square or rectangular).\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e \u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eIf present, the openings of the glass substrate may be intended to be further processed with metal fillings.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e \u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThe glass substrate is intended to remain permanently in the package or device.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e \u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eMethods of measurements suitable for determining the characteristics in this Specification are indicated.\u003c\/font\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e \u003c\/p\u003e\u003cfont face=\"arial\" size=\"2\"\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e (purchase separately)\u003c\/font\u003e\u003cp\u003e\u003cfont face=\"arial\" size=\"2\"\u003eSEMI 3D7 — Guide for Alignment Mark for 3DS-IC Process\u003cbr\u003eSEMI 3D11 — Terminology for Through Glass Via and Blind Via in Glass Geometrical Metrology\u003cbr\u003eSEMI 3D12 — Guide on Measuring Flatness and Shape of Low Stiffness Substrates\u003cbr\u003eSEMI E119 — Mechanical Specification for Reduced-Pitch Front-Opening Box for Interfactory Transport of 300 mm Wafers\u003cbr\u003eSEMI G90 — Specification for 300 mm Wafer Coin-Stack Type Shipping Container Used for Test and Packaging Processes\u003cbr\u003eSEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers\u003cbr\u003eSEMI M31 — Mechanical Specification for Front-Opening Shipping Box Used to Transport and Ship 300 mm Wafers\u003cbr\u003eSEMI M35 — Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection\u003cbr\u003eSEMI M40 — Guide for Measurement of Roughness of Planar Surfaces on Polished Wafers\u003cbr\u003eSEMI M45 — Specification for 300 mm Wafer Shipping System\u003cbr\u003eSEMI M59 — Terminology for Silicon Technology\u003cbr\u003eSEMI MF533 — Test Method for Thickness and Thickness Variation of Silicon Wafers\u003cbr\u003eSEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning\u003cbr\u003eSEMI MF671 — Test Method for Measuring Flat Length on Wafers of Silicon and Other Electronic Materials\u003cbr\u003eSEMI MF928 — Test Method for Edge Contour of Circular Semiconductor Wafers and Rigid Disk Substrates\u003cbr\u003eSEMI MF1152 — Test Method for Dimensions of Notches on Silicon Wafers\u003cbr\u003eSEMI MF1390 — Test Method for Measuring Bow and Warp on Silicon Wafers by Automated Noncontact Scanning\u003cbr\u003eSEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning\u003cbr\u003eSEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Noncontact Scanning\u003cbr\u003eSEMI MF2074 — Guide for Measuring Diameter of Silicon and Other Semiconductor Wafers\u003cbr\u003eSEMI MS1 — Guide to Specifying Wafer-Wafer Bonding Alignment Targets\u003cbr\u003eSEMI T7 — Specification for Back Surface Marking of Double-sided Polished Wafers with a Two-Dimensional Matrix Code Symbol\u003cbr\u003e\u003cbr\u003e\u003cb\u003eRevision History\u003c\/b\u003e\u003cbr\u003eSEMI 3D16-0822 (technical revision)\u003cbr\u003eSEMI 3D16-1116 (first published)\u003c\/font\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI 3D16-0822 - Current","offer_id":40234234970179,"sku":"15220","price":193.0,"currency_code":"USD","in_stock":true},{"title":"SEMI 3D16-1116 - Superseded","offer_id":40234235002947,"sku":"997","price":193.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/3DVolume_24795202-a69b-4022-a3b6-c60ce086bef1.png?v=1776703136"},{"product_id":"3d00600-semi-3d6-guide-for-cmp-and-micro-bump-processes-for-frontside-through-silicon-via-tsv-integration","title":"3D00600 - SEMI 3D6 - Guide for CMP and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration","description":"\u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eIn order to speed up volume production of 3DS-IC products, a generic middle-end process flow is needed to communicate the frontend and backend processes. The quality criteria and metrology methodology of the key modules such as TSV, chemical mechanical planarization (CMP), and micro-bump are developed to ensure high-yield of the middle-end process. Therefore, this guide provides a generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump. The guide will provide criteria and common baselines of the middle-end process for related upstream and downstream manufacturers in fabricating 3DS-IC products.\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e　\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Guide proposes a frontside TSV integration scheme as one of the generic middle-end process flow. The flow includes steps such as TSV formation, RDL formation, CMP, temporary carrier bonding, wafer thinning, micro-bump formation, and carrier debonding.\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e　\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Guide define acceptable CMP criteria of TSV in terms of dishing, erosion, and voids. CMP criteria can be determined by metrology technology in both contact methods such as: micro profilometer; 4-points resistivity probes; or non-contact methods (e.g., ultrasonic scan mapping, Coherence Interferometry, or other laser-based light scattering detection schemes). TSV formation and reveal are significantly dependent on the performance of CMP process. The outcome of the high CMP quality yields better TSV connectivity.\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e　\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003eThis Guide provides criteria for measurement methodology for micro-bump dimensions, including sampling rate, sampling sites and mapping, reference datum, and survey available metrology tools. The outcome will be an important bridge communication among IC design firms, fabs, and packaging houses. The assumption of wafer-to-wafer (W2W), chip-to-wafer (C2W) and chip-to-chip (C2C) are that testing data is available for known test good die.\u003c\/font\u003e\u003c\/p\u003e \u003cp align=\"left\"\u003e\u003c\/p\u003e\u003cp dir=\"ltr\" align=\"justify\"\u003e\u003cfont face=\"arial\" size=\"2\"\u003e　\u003c\/font\u003e\u003c\/p\u003e\u003cfont face=\"arial\" size=\"2\"\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e\u003cbr\u003e\u003c\/font\u003e\u003cp\u003e\u003cfont face=\"arial\" size=\"2\"\u003eSEMI 3D1 — Terminology for Through Silicon Via Geometrical Metrology\u003cbr\u003e SEMI M59 — Terminology for Silicon Technology\u003c\/font\u003e\u003cbr\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI 3D6-0619 - Current","offer_id":40234235527235,"sku":"11151","price":193.0,"currency_code":"USD","in_stock":true},{"title":"SEMI 3D6-0913 - Superseded","offer_id":40234235592771,"sku":"1004","price":193.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/3DVolume_88c2cccd-12ed-4cb5-a32c-44348945cb62.png?v=1776703144"},{"product_id":"3d00700-semi-3d7-guide-for-alignment-mark-for-3ds-ic-process","title":"3D00700 - SEMI 3D7 - Guide for Alignment Mark for 3DS-IC Process","description":"\u003cp align=\"justify\"\u003e\u003cbr\u003e\u003c\/p\u003e\u003cp align=\"justify\"\u003e\u003c\/p\u003e\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003ePhoto alignment mark configuration is the key to ensure\nconsistent and precise alignment of layers, chips, and wafers. Therefore, this\nGuide provides the alignment mark strategy for chip to chip, chip to wafer, and\nwafer to wafer stacking. This Guide also addresses the universal alignment mark\nwhere the outcome will be a feasible photo alignment standard.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cbr\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eDefine and develop lithography alignment strategy for C2C, C2W\nand W2W stacking. The alignment mark is preferable to be implemented at frontside\nfinal metal and\/or backside metal layer masking. This Guide addresses universal\nalignment mark, including shape, dimension, and location. The outcome of a\nfeasible photo alignment standard will be critical to the C2C, C2W and W2W\nstacking.\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eReferenced SEMI Standards\u003c\/b\u003e (purchase separately)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI M20 — Practice for Establishing a Wafer Coordinate\nSystem \u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI MS1 — Guide to Specifying Wafer-Wafer Bonding\nAlignment Targets\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003co:p\u003e \u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003e\u003cb\u003eRevision History\u003c\/b\u003e\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI 3D7-0913 (Reapproved 0219)\u003co:p\u003e\u003c\/o:p\u003e\u003c\/span\u003e\u003c\/p\u003e\n\n\u003cp class=\"MsoNormal\"\u003e\u003cspan style='font-size:10.0pt;line-height:107%;font-family:\n\"Arial\",sans-serif'\u003eSEMI 3D7-0913 (first published)\u003c\/span\u003e\u003c\/p\u003e","brand":"semi.org","offers":[{"title":"SEMI 3D7-0913 (Reapproved 0219) - Current","offer_id":40234242342979,"sku":"6170","price":193.0,"currency_code":"USD","in_stock":true},{"title":"SEMI 3D7-0913 - Superseded","offer_id":40234242375747,"sku":"1005","price":193.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0567\/3402\/3747\/files\/3DVolume_524bca2b-8387-426e-a436-5c5779e556ce.png?v=1776703143"}],"url":"https:\/\/store-dev2.semi.org\/collections\/individual-semi-standards.oembed","provider":"SEMI Dev 2","version":"1.0","type":"link"}